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» Empirical Design of Geometric Algorithms
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DAC
2009
ACM
15 years 6 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
GECCO
2007
Springer
268views Optimization» more  GECCO 2007»
15 years 6 months ago
Vulnerability analysis and security framework (BeeSec) for nature inspired MANET routing protocols
Design, development and evaluation of adaptive, scalable, and power aware Bio/Nature inspired routing protocols has received a significant amount of attention in the recent past....
Nauman Mazhar, Muddassar Farooq
KDD
2008
ACM
174views Data Mining» more  KDD 2008»
16 years 5 days ago
Effective label acquisition for collective classification
Information diffusion, viral marketing, and collective classification all attempt to model and exploit the relationships in a network to make inferences about the labels of nodes....
Mustafa Bilgic, Lise Getoor
SENSYS
2006
ACM
15 years 5 months ago
ATPC: adaptive transmission power control for wireless sensor networks
Extensive empirical studies presented in this paper confirm that the quality of radio communication between low power sensor devices varies significantly with time and environme...
Shan Lin, Jingbin Zhang, Gang Zhou, Lin Gu, John A...
ISQED
2007
IEEE
127views Hardware» more  ISQED 2007»
15 years 6 months ago
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Ch...