Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Design, development and evaluation of adaptive, scalable, and power aware Bio/Nature inspired routing protocols has received a significant amount of attention in the recent past....
Information diffusion, viral marketing, and collective classification all attempt to model and exploit the relationships in a network to make inferences about the labels of nodes....
Extensive empirical studies presented in this paper confirm that the quality of radio communication between low power sensor devices varies significantly with time and environme...
Shan Lin, Jingbin Zhang, Gang Zhou, Lin Gu, John A...
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...