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» Employing Simulation to Evaluate Designs: The APEX Approach
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ISPASS
2010
IEEE
15 years 6 months ago
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads
Abstract—We generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: 1) huge simulation time (weeks to m...
Karthik Ganesan, Jungho Jo, Lizy K. John
KDD
2008
ACM
206views Data Mining» more  KDD 2008»
16 years 6 days ago
Identifying biologically relevant genes via multiple heterogeneous data sources
Selection of genes that are differentially expressed and critical to a particular biological process has been a major challenge in post-array analysis. Recent development in bioin...
Zheng Zhao, Jiangxin Wang, Huan Liu, Jieping Ye, Y...
LCTRTS
2007
Springer
15 years 6 months ago
External memory page remapping for embedded multimedia systems
As memory speeds and bus capacitances continue to rise, external memory bus power will make up an increasing portion of the total system power budget for system-on-a-chip embedded...
Ke Ning, David R. Kaeli
ECLIPSE
2006
ACM
15 years 5 months ago
HAM: cross-cutting concerns in Eclipse
As programs evolve, newly added functionality sometimes no longer aligns with the original design, ending up scattered across the software system. Aspect mining tries to identify ...
Silvia Breu, Thomas Zimmermann, Christian Lindig
VEE
2005
ACM
140views Virtualization» more  VEE 2005»
15 years 5 months ago
Planning for code buffer management in distributed virtual execution environments
Virtual execution environments have become increasingly useful in system implementation, with dynamic translation techniques being an important component for performance-critical ...
Shukang Zhou, Bruce R. Childers, Mary Lou Soffa