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VTS
2000
IEEE
167views Hardware» more  VTS 2000»
15 years 2 months ago
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukher...
74
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FPL
2003
Springer
65views Hardware» more  FPL 2003»
15 years 3 months ago
Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits
Matteo Sonza Reorda, Massimo Violante
ISVLSI
2006
IEEE
129views VLSI» more  ISVLSI 2006»
15 years 4 months ago
Dependability Analysis of Nano-scale FinFET circuits
FinFET technology has been proposed as a promising alternative for deep sub-micro bulk CMOS technology, because of its better scalability. Previous work have studied the performan...
Feng Wang 0004, Yuan Xie, Kerry Bernstein, Yan Luo