Sciweavers

4 search results - page 1 / 1
» Enabling certification for dynamic partial reconfiguration u...
Sort
View
77
Voted
DATE
2007
IEEE
92views Hardware» more  DATE 2007»
15 years 11 months ago
Enabling certification for dynamic partial reconfiguration using a minimal flow
Bertrand Rousseau, Philippe Manet, D. Galerin, D. ...
156
Voted
CODES
2009
IEEE
15 years 9 months ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...
ARCS
2006
Springer
15 years 8 months ago
Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro
Today's FPGAs (Field Programmable Gate Arrays) are widely used, but not to their full potential. In Virtex series FPGAs from Xilinx a special feature, the dynamic and partial...
Christopher Claus, Florian Helmut Müller, Wal...
CGO
2003
IEEE
15 years 8 months ago
Optimal and Efficient Speculation-Based Partial Redundancy Elimination
Existing profile-guided partial redundancy elimination (PRE) methods use speculation to enable the removal of partial redundancies along more frequently executed paths at the expe...
Qiong Cai, Jingling Xue