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» Encoding Algorithms for Logic Synthesis
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DATE
2004
IEEE
144views Hardware» more  DATE 2004»
15 years 8 months ago
Smaller Two-Qubit Circuits for Quantum Communication and Computation
We show how to implement an arbitrary two-qubit unitary operation using any of several quantum gate libraries with small a priori upper bounds on gate counts. In analogy to librar...
Vivek V. Shende, Igor L. Markov, Stephen S. Bulloc...
FPGA
2006
ACM
155views FPGA» more  FPGA 2006»
15 years 8 months ago
Improvements to technology mapping for LUT-based FPGAs
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
ISLPED
2010
ACM
206views Hardware» more  ISLPED 2010»
15 years 4 months ago
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija
ATAL
2005
Springer
15 years 10 months ago
Bounded model checking knowledge and branching time in synchronous multi-agent systems
We present an approach to the verification of temporal epistemic properties in synchronous multi-agent systems (MAS) via bounded model checking (BMC). Based on the semantics of s...
Xiangyu Luo, Kaile Su, Abdul Sattar, Qingliang Che...
DAC
2006
ACM
16 years 5 months ago
SAT sweeping with local observability don't-cares
SAT sweeping is a method for simplifying an AND/INVERTER graph (AIG) by systematically merging graph vertices from the inputs towards the outputs using a combination of structural...
Qi Zhu, Nathan Kitchen, Andreas Kuehlmann, Alberto...