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HIPEAC
2011
Springer
14 years 2 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
149
Voted
DAC
2003
ACM
16 years 3 months ago
Accurate timing analysis by modeling caches, speculation and their interaction
Schedulability analysis of real-time embedded systems requires worst case timing guarantees of embedded software performance. This involves not only language level program analysi...
Xianfeng Li, Tulika Mitra, Abhik Roychoudhury
ICECCS
2000
IEEE
87views Hardware» more  ICECCS 2000»
15 years 6 months ago
Automated Result Verification with AWK
The goal of result-verificationis toprove that one execution run of a program satisjes its speciJcation. Compared with iniplenzentation-verification,result-verification has a larg...
Balkhis Abu Bakar, Tomasz Janowski
CEC
2003
IEEE
15 years 7 months ago
An evolutionary approach for reducing the switching activity in address buses
In this paper we present two new approaches based on genetic algorithms (GA) to reduce power consumption by communication buses in an embedded system. The first approach makes it ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
ISMB
1993
15 years 3 months ago
Discovering Sequence Similarity by the Algorithmic Significance Method
The minimal-length encoding approach is applied to define concept of sequence similarity. Asequence is defined to be similar to another sequence or to a set of keywords if it can ...
Aleksandar Milosavljevic