4722 search results - page 444 / 945 » Encoding Program Executions |
123
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IPPS
2003
IEEE
15 years 11 months ago
2003
IEEE
In this paper, we overview general hardware architecture and a programming model of SRC-6ETM reconfigurable computers, and compare the performance of the SRC-6E machine vs. IntelÂ...
144
Voted
ICPP
1999
IEEE
15 years 10 months ago
1999
IEEE
Trace-level reuse is based on the observation that some traces (dynamic sequences of instructions) are frequently repeated during the execution of a program, and in many cases, th...
160
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RTSS
1999
IEEE
15 years 10 months ago
1999
IEEE
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
192
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SPIN
2000
Springer
15 years 10 months ago
2000
Springer
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...
159
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AOSD
2009
ACM
15 years 9 months ago
2009
ACM
In this paper we present a generic, mirror-based debugging architecture that supports runtime visibility and traceability of aspect oriented (AO) software systems. Runtime visibil...