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» Encoding Program Executions
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EDBTW
2010
Springer
15 years 7 months ago
Declarative scheduling in highly scalable systems
In modern architectures based on Web Services or Cloud Computing, a very large number of user requests arrive concurrently and has to be scheduled for execution constrained by cor...
Christian Tilgner
ISCA
2010
IEEE
189views Hardware» more  ISCA 2010»
15 years 7 months ago
RETCON: transactional repair without replay
Over the past decade there has been a surge of academic and industrial interest in optimistic concurrency, i.e. the speculative parallel execution of code regions that have the se...
Colin Blundell, Arun Raghavan, Milo M. K. Martin
DSN
2002
IEEE
15 years 7 months ago
Detecting Processor Hardware Faults by Means of Automatically Generated Virtual Duplex Systems
A virtual duplex system (VDS) can be used to increase safety without the use of structural redundancy on a single machine. If a deterministic program P is calculating a given func...
Markus Jochim
FCCM
2002
IEEE
127views VLSI» more  FCCM 2002»
15 years 7 months ago
Hardware-Assisted Fast Routing
To fully realize the benefits of partial and rapid reconfiguration of field-programmable devices, we often need to dynamically schedule computing tasks and generate instance-sp...
André DeHon, Randy Huang, John Wawrzynek
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
15 years 7 months ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Ho-Seop Kim, James E. Smith