The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
We present techniques to create convincing high-quality watercolor illustrations of plants. Mainly focusing on the real-time rendering, we introduce methods to abstract the visual...
Database application programs typically contain program units that use SQL statements to manipulate records in database instances. Testing the correctness of data manipulation by ...
In this paper we show how to extend Coloured Petri Nets (CP-nets), with three new modelling primitives—place capacities, test arcs and inhibitor arcs. The new modelling primitiv...