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ISPASS
2010
IEEE
15 years 6 months ago
Hardware prediction of OS run-length for fine-grained resource customization
—In the past ten years, computer architecture has seen a paradigm shift from emphasizing single thread performance to energy efficient, throughput oriented, chip multiprocessors...
David Nellans, Kshitij Sudan, Rajeev Balasubramoni...
CODES
2008
IEEE
15 years 6 months ago
Distributed and low-power synchronization architecture for embedded multiprocessors
In this paper we present a framework for a distributed and very low-cost implementation of synchronization controllers and protocols for embedded multiprocessors. The proposed arc...
Chenjie Yu, Peter Petrov
CASES
2007
ACM
15 years 3 months ago
Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms
Many MPSoC applications are loop-intensive and amenable to automatic parallelization with suitable compiler support. One of the key components of any compiler-parallelized code is...
Andrea Marongiu, Luca Benini, Mahmut T. Kandemir
CODES
2001
IEEE
15 years 3 months ago
A constraint-based application model and scheduling techniques for power-aware systems
New embedded systems must be power-aware, not just low-power. That is, they must track their power sources and the changingpower and performance constraints imposed by the environ...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi ...
HIPEAC
2010
Springer
15 years 1 months ago
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions
Abstract. Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include...
Theo Kluter, Samuel Burri, Philip Brisk, Edoardo C...