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156
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DATE
2005
IEEE
15 years 11 months ago
2005
IEEE
We present a novel, quality-driven, architectural-level approach that trades-off the output quality to enable power-aware processing of multimedia streams. The error tolerance of ...
166
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EUROPAR
2005
Springer
15 years 11 months ago
2005
Springer
Instruction delivery is a critical component for wide-issue processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and ba...
147
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ISHPC
2003
Springer
15 years 11 months ago
2003
Springer
Abstract. In SMT processors several threads run simultaneously to increase available ILP, sharing but competing for resources. The instruction fetch policy plays a key role, determ...
119
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
—In state of the art systems, workload scheduling and server fan speed operate independently leading to cooling inefficiencies. In this work we propose GentleCool, a proactive m...
171
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...