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RTSS
1998
IEEE
15 years 1 months ago
Synthesis Techniques for Low-Power Hard Real-Time Systems on Variable Voltage Processors
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...
Inki Hong, Gang Qu, Miodrag Potkonjak, Mani B. Sri...
RTS
2011
131views more  RTS 2011»
14 years 4 months ago
Global scheduling based reliability-aware power management for multiprocessor real-time systems
Reliability-aware power management (RAPM) has been a recent research focus due the negative effects of the popular power management technique dynamic voltage and frequency scaling ...
Xuan Qi, Dakai Zhu, Hakan Aydin
VLSISP
2008
132views more  VLSISP 2008»
14 years 9 months ago
Scenario Selection and Prediction for DVS-Aware Scheduling of Multimedia Applications
Modern multimedia applications usually have real-time constraints and they are implemented using application-domain specific embedded processors. Dimensioning a system requires acc...
Stefan Valentin Gheorghita, Twan Basten, Henk Corp...
IPPS
2008
IEEE
15 years 3 months ago
A simple power-aware scheduling for multicore systems when running real-time applications
High-performance microprocessors, e.g., multithreaded and multicore processors, are being implemented in embedded real-time systems because of the increasing computational require...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...
IPCCC
2006
IEEE
15 years 3 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John