23 search results - page 3 / 5 » Energy and latency evaluation of NoC topologies |
HPCA
2009
IEEE
15 years 11 months ago
2009
IEEE
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
80
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SC
2009
ACM
15 years 5 months ago
2009
ACM
The present contribution explores the design space for virtual channel (VC) and switch allocators in network-on-chip (NoC) routers. Based on detailed RTL-level implementations, we...
119
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ICPP
2007
IEEE
15 years 5 months ago
2007
IEEE
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length ...
SBCCI
2005
ACM
15 years 4 months ago
2005
ACM
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
118
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NOCS
2008
IEEE
15 years 5 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...