2 search results - page 1 / 1 » Energy efficient implementation of parallel CMOS multipliers... |
82
Voted
ISLPED
2010
ACM
14 years 10 months ago
2010
ACM
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
ICCAD
2008
IEEE
15 years 7 months ago
2008
IEEE
—To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nanoelect...