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» Energy efficient packet classification hardware accelerator
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PERCOM
2007
ACM
15 years 9 months ago
Practical Exploitation of the Energy-Latency Tradeoff for Sensor Network Broadcast
As devices become more reliant on battery power, it is essential to design energy efficient protocols. While there is a vast amount of research into power save protocols for unicas...
Matthew J. Miller, Indranil Gupta
IJSNET
2008
118views more  IJSNET 2008»
14 years 9 months ago
Public key cryptography empowered smart dust is affordable
: Public key cryptography (PKC) has been considered for a long time to be computationally too expensive for small battery powered devices. However, PKC turned out to be very benefi...
Steffen Peter, Peter Langendörfer, Krzysztof ...
81
Voted
FPL
2006
Springer
105views Hardware» more  FPL 2006»
15 years 1 months ago
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
K. Van Renterghem, Dieter Verhulst, S. Verschuere,...
90
Voted
FPL
2010
Springer
180views Hardware» more  FPL 2010»
14 years 7 months ago
A Karatsuba-Based Montgomery Multiplier
Abstract--Modular multiplication of long integers is an important building block for cryptographic algorithms. Although several FPGA accelerators have been proposed for large modul...
Gary Chun Tak Chow, Ken Eguro, Wayne Luk, Philip L...
COMPUTING
2004
204views more  COMPUTING 2004»
14 years 9 months ago
Image Registration by a Regularized Gradient Flow. A Streaming Implementation in DX9 Graphics Hardware
The presented image registration method uses a regularized gradient flow to correlate the intensities in two images. Thereby, an energy functional is successively minimized by des...
Robert Strzodka, Marc Droske, Martin Rumpf