Sciweavers

122 search results - page 14 / 25
» Energy reduction in multiprocessor systems using transaction...
Sort
View
IISWC
2008
IEEE
15 years 6 months ago
Temporal streams in commercial server applications
Commercial server applications remain memory bound on modern multiprocessor systems because of their large data footprints, frequent sharing, complex non-strided access patterns, ...
Thomas F. Wenisch, Michael Ferdman, Anastasia Aila...
99
Voted
CODES
2007
IEEE
15 years 6 months ago
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
Brett H. Meyer, Donald E. Thomas
ISCAS
2005
IEEE
113views Hardware» more  ISCAS 2005»
15 years 5 months ago
Effect of traffic localization on energy dissipation in NoC-based interconnect
Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend of SoC design. Scaleable communication-centric interconnect fabrics such as networks-onchip (No...
Partha Pratim Pande, Cristian Grecu, Michael Jones...
ASPLOS
2008
ACM
15 years 1 months ago
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-...
112
Voted
HIPEAC
2010
Springer
15 years 1 months ago
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions
Abstract. Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include...
Theo Kluter, Samuel Burri, Philip Brisk, Edoardo C...