114 search results - page 15 / 23 » Energy-efficient FPGA interconnect design |
ASPDAC
2005
ACM
15 years 3 months ago
2005
ACM
In this paper, we propose a new multi-objective multilevel K-way partitioning which is aware of resource utilization distribution, assuming the resource utilization for a partitio...
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
We propose two new FPGA routing switch designs that are programmable to operate in three different modes: highspeed, low-power or sleep. High-speed mode provides similar power an...
FPL
2000
Springer
15 years 1 months ago
2000
Springer
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
TC
1998
14 years 9 months ago
1998
—The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational fau...
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GLVLSI
2003
IEEE
15 years 2 months ago
2003
IEEE
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of...