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» Energy-efficient FPGA interconnect design
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FCCM
2009
IEEE
171views VLSI» more  FCCM 2009»
15 years 4 months ago
Accelerating SPICE Model-Evaluation using FPGAs
—Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SP...
Nachiket Kapre, André DeHon
FPGA
2004
ACM
158views FPGA» more  FPGA 2004»
15 years 3 months ago
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
Michalis D. Galanis, George Theodoridis, Spyros Tr...
FPGA
2000
ACM
141views FPGA» more  FPGA 2000»
15 years 1 months ago
Tolerating operational faults in cluster-based FPGAs
In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain ...
Vijay Lakamraju, Russell Tessier
82
Voted
DATE
2006
IEEE
110views Hardware» more  DATE 2006»
15 years 3 months ago
Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications
This paper presents the design and full prototype implementation of a configurable multiprocessor platform that supports distributed execution of applications described in UML 2.0...
Tero Arpinen, Petri Kukkala, Erno Salminen, Marko ...
FPL
2009
Springer
101views Hardware» more  FPL 2009»
15 years 2 months ago
An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper...
Tobias Schumacher, Christian Plessl, Marco Platzne...