Sciweavers

114 search results - page 21 / 23
» Energy-efficient FPGA interconnect design
Sort
View
DATE
2002
IEEE
206views Hardware» more  DATE 2002»
15 years 2 months ago
Accurate Area and Delay Estimators for FPGAs
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
Anshuman Nayak, Malay Haldar, Alok N. Choudhary, P...
ISCA
2007
IEEE
106views Hardware» more  ISCA 2007»
15 years 3 months ago
Architectural implications of brick and mortar silicon manufacturing
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, ...
DATE
2010
IEEE
168views Hardware» more  DATE 2010»
15 years 2 months ago
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
Luca Sterpone, Niccolò Battezzati
EXPCS
2007
15 years 1 months ago
RiceNIC: a reconfigurable network interface for experimental research and education
The evaluation of new network server architectures is usually performed experimentally using either a simulator or a hardware prototype. Accurate simulation of the hardwaresoftwar...
Jeffrey Shafer, Scott Rixner
CSB
2004
IEEE
123views Bioinformatics» more  CSB 2004»
15 years 1 months ago
A New Hardware Architecture for Genomic and Proteomic Sequence Alignment
We describe a novel hardware architecture for genomic and proteomic sequence alignment which achieves a speed-up of two to three orders of magnitude over Smith-Waterman dynamic pr...
Greg Knowles, Paul Gardner-Stephen