114 search results - page 5 / 23 » Energy-efficient FPGA interconnect design |
DAC
2000
ACM
15 years 10 months ago
2000
ACM
67
Voted
FPGA
2004
ACM
15 years 3 months ago
2004
ACM
FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better ...
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
GLVLSI
2008
IEEE
14 years 9 months ago
2008
IEEE
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
82
Voted
DAC
2003
ACM
15 years 2 months ago
2003
ACM
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...