As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
Vijay Raghunathan, Mani B. Srivastava, Rajesh K. G...
—The dynamic programmable logic array (PLA) style has become popular in designing high-performance microprocessors because of its high speed and predictable routing delay. Howeve...
Presented in this paper are 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy...