67 search results - page 3 / 14 » Enhanced Code Compression for Embedded RISC Processors |
ISCAS
2007
IEEE
14 years 21 days ago
2007
IEEE
— A flexible transport stream processor for DTV which is also designed under cost-effective consideration is proposed in this paper. A RISC micro-controller is allocated as the ...
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the domi...
SAC
2005
ACM
13 years 12 months ago
2005
ACM
We present a tool which is designed to be used as a code compression advisory system for object code to be run on an embedded processor. All the compression schemes support run-ti...
MICRO
2002
IEEE
13 years 11 months ago
2002
IEEE
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
ASYNC
1998
IEEE
13 years 10 months ago
1998
IEEE
This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs a...