60 search results - page 3 / 12 » Enhancing the effectiveness of utilizing an instruction regi... |
DSN
2009
IEEE
2009
IEEE
Processor reliability enhancement through compiler-directed register file peak temperature reduction
13 years 10 months ago
Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliab...
ICCD
2004
IEEE
14 years 3 months ago
2004
IEEE
Modern superscalar microprocessors need sizable register files to support large number of in-flight instructions for exploiting ILP. An alternative to building large register file...
ICPP
2006
IEEE
14 years 11 days ago
2006
IEEE
We propose a series of aggressive register deallocation mechanisms to reduce the register file pressure and increase the parallelism exploited by superscalar microprocessors. Our ...
ASPDAC
2008
ACM
13 years 8 months ago
2008
ACM
In this paper we describe load scheduling, a novel method that balances load among register files by residual resources. Load scheduling can reduce register pressure for clustered...
PACS
2004
Springer
13 years 11 months ago
2004
Springer
In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a ...