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VTS
2003
IEEE
115views Hardware» more  VTS 2003»
15 years 3 months ago
Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs
Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimizati...
Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Kr...
ICCD
2003
IEEE
140views Hardware» more  ICCD 2003»
15 years 7 months ago
Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems
NAND flash memory has become an indispensable component in embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cos,t and high d...
Chanik Park, Jaeyu Seo, Dongyoung Seo, Shinhan Kim...
RTCSA
2005
IEEE
15 years 4 months ago
Optimization of Hierarchically Scheduled Heterogeneous Embedded Systems
We present an approach to the analysis and optimization of heterogeneous distributed embedded systems for hard real-time applications. The systems are heterogeneous not only in te...
Traian Pop, Paul Pop, Petru Eles, Zebo Peng
66
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DATE
2004
IEEE
147views Hardware» more  DATE 2004»
15 years 2 months ago
Automatic Tuning of Two-Level Caches to Embedded Applications
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
PATMOS
2000
Springer
15 years 2 months ago
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications
Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, esp...
Dimitrios Soudris, Nikolaos D. Zervas, Antonios Ar...