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HPCC
2009
Springer
15 years 3 months ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
91
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ICDM
2006
IEEE
176views Data Mining» more  ICDM 2006»
15 years 4 months ago
Razor: mining distance-constrained embedded subtrees
Due to their capability for expressing semantics and relationships among data objects, semi-structured documents have become a common way of representing domain knowledge. Compari...
Henry Tan, Tharam S. Dillon, Fedja Hadzic, Elizabe...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 3 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
ASPLOS
2006
ACM
15 years 4 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal
CODES
2002
IEEE
15 years 3 months ago
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management
The aggressive evolution of the semiconductor industry — smaller process geometries, higher densities, and greater chip complexity — has provided design engineers the means to...
Mohamed Shalan, Vincent John Mooney III