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SIGMETRICS
1997
ACM
111views Hardware» more  SIGMETRICS 1997»
15 years 1 months ago
Cache Behavior of Network Protocols
In this paper we present a performance study of memory reference behavior in network protocol processing, using an Internet-based protocol stack implemented in the x-kernel runnin...
Erich M. Nahum, David J. Yates, James F. Kurose, D...
CPHYSICS
2007
71views more  CPHYSICS 2007»
14 years 9 months ago
Simulation of n-qubit quantum systems. III. Quantum operations
During the last decade, several quantum information protocols, such as quantum key distribution, teleportation or quantum computation, have attracted a lot of interest. Despite th...
T. Radtke, S. Fritzsche
DAC
2008
ACM
15 years 10 months ago
Miss reduction in embedded processors through dynamic, power-friendly cache design
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
Garo Bournoutian, Alex Orailoglu
DATE
2007
IEEE
124views Hardware» more  DATE 2007»
15 years 4 months ago
Worst-case design and margin for embedded SRAM
An important aspect of Design for Yield for embedded SRAM is identifying the expected worst case behavior in order to guarantee that sufficient design margin is present. Previousl...
Robert C. Aitken, Sachin Idgunji
CODES
2000
IEEE
15 years 2 months ago
Heuristic tradeoffs between latency and energy consumption in register assignment
One of the challenging tasks in code generation for embedded systems is register allocation and assignment, wherein one decides on the placement and lifetimes of variables in regi...
R. Anand, Margarida F. Jacome, Gustavo de Veciana