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115
Voted
GC
2010
Springer
14 years 11 months ago
2010
Springer
In 1966 Barnette introduced a set of graphs, called circuit graphs, which are obtained from 3-connected planar graphs by deleting a vertex. Circuit graphs and 3-connected planar g...
119
Voted
FPGA
2010
ACM
15 years 10 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...