43 search results - page 7 / 9 » Equivalence Checking of Reversible Circuits |
113
Voted
DATE
1999
IEEE
15 years 2 months ago
1999
IEEE
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalen...
98
Voted
GLVLSI
2007
IEEE
15 years 2 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
89
Voted
ATVA
2005
Springer
15 years 3 months ago
2005
Springer
Abstract. This paper argues that flatness appears as a central notion in the verification of counter automata. A counter automaton is called flat when its control graph can be ...
76
Voted
ICCD
2006
IEEE
15 years 7 months ago
2006
IEEE
— We have entered an era where chip yields are decreasing with scaling. A new concept called intelligible testing has been previously proposed with the goal of reversing this tre...
80
Voted
DAC
2001
ACM
15 years 11 months ago
2001
ACM
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit...