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» Error Correction Based on Verification Techniques
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CONCUR
2006
Springer
15 years 1 months ago
Sanity Checks in Formal Verification
One of the advantages of temporal-logic model-checking tools is their ability to accompany a negative answer to the correctness query by a counterexample to the satisfaction of the...
Orna Kupferman
GLVLSI
2008
IEEE
150views VLSI» more  GLVLSI 2008»
14 years 9 months ago
Using unsatisfiable cores to debug multiple design errors
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...
André Sülflow, Görschwin Fey, Rod...
COMCOM
2000
97views more  COMCOM 2000»
14 years 9 months ago
Verification of security protocols using LOTOS-method and application
We explain how the formal language LOTOS can be used to specify security protocols and cryptographic operations. We describe how security properties can be modelled as safety prop...
Guy Leduc, François Germeau
ICSE
2005
IEEE-ACM
15 years 9 months ago
Automatic generation and maintenance of correct spreadsheets
Existing spreadsheet systems allow users to change cells arbitrarily, which is a major source of spreadsheet errors. We propose a system that prevents errors in spreadsheets by re...
Martin Erwig, Robin Abraham, Irene Cooperstein, St...
CADE
2009
Springer
15 years 10 months ago
Integrated Reasoning and Proof Choice Point Selection in the Jahob System - Mechanisms for Program Survival
In recent years researchers have developed a wide range of powerful automated reasoning systems. We have leveraged these systems to build Jahob, a program specification, analysis, ...
Martin C. Rinard