1534 search results - page 110 / 307 » Error Reporting Logic |
165
click to vote
IVC
2008
15 years 3 months ago
2008
A framework for the logical and statistical analysis and annotation of dynamic scenes containing occlusion and other uncertainties is presented. This framework consists of three e...
136
click to vote
ICCAD
2007
IEEE
15 years 10 months ago
2007
IEEE
—In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamic...
130
click to vote
TACAS
2005
Springer
15 years 9 months ago
2005
Springer
We present MC2 , what we believe to be the first randomized, Monte Carlo algorithm for temporal-logic model checking, the classical problem of deciding whether or not a property s...
217
click to vote
IPPS
2003
IEEE
15 years 9 months ago
2003
IEEE
Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of tra...
131
click to vote
ICSE
2001
IEEE-ACM
15 years 8 months ago
2001
IEEE-ACM
Mocha is a model checker based on the theme of exploiting design modularity: instead of manipulating unstructured state-transition graphs, it supports the hierarchical modeling fra...