1534 search results - page 12 / 307 » Error Reporting Logic |
100
click to vote
GLVLSI
2010
IEEE
15 years 3 months ago
2010
IEEE
Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising directio...
ITC
2003
IEEE
15 years 3 months ago
2003
IEEE
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...
GLVLSI
2007
IEEE
15 years 1 months ago
2007
IEEE
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
BELL
2000
14 years 9 months ago
2000
A significant part of the call processing software for Lucent's new PathStar access server [FSW98] was checked with automated formal verification techniques. The verification...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
There is a growing concern about timing errors resulting from design marginalities and the effects of circuit aging on speed-paths in logic circuits. This paper presents a low ove...