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ICPPW
2008
IEEE
15 years 11 months ago
Replay-Based Synchronization of Timestamps in Event Traces of Massively Parallel Applications
Event traces are helpful in understanding the performance behavior of message-passing applications since they allow in-depth analyses of communication and synchronization patterns...
Daniel Becker, John C. Linford, Rolf Rabenseifner,...
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
15 years 10 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
DATE
2002
IEEE
206views Hardware» more  DATE 2002»
15 years 9 months ago
Accurate Area and Delay Estimators for FPGAs
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
Anshuman Nayak, Malay Haldar, Alok N. Choudhary, P...
DSD
2004
IEEE
136views Hardware» more  DSD 2004»
15 years 8 months ago
FPGA Based Design of the Railway's Interlocking Equipments
This paper describes the architecture of a safety system of the railway's interlocking equipment, which has been developed for Czech railways. The system will be used for the...
Radek Dobias, Hana Kubatova
WSPI
2008
15 years 5 months ago
Semantics of Information as Interactive Computation
Computers today are not only the calculation tools - they are directly (inter)acting in the physical world which itself may be conceived of as the universal computer (Zuse, Fredkin...
Gordana Dodig-Crnkovic