1534 search results - page 197 / 307 » Error Reporting Logic |
124
Voted
TCAD
1998
15 years 14 days ago
1998
—This paper addresses, from a probabilistic point of view, the issue of switching activity estimation in combinational circuits under the zero-delay model. As the main theoretica...
78
Voted
DAC
2002
ACM
16 years 1 months ago
2002
ACM
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
87
Voted
SIGSOFT
2003
ACM
16 years 1 months ago
2003
ACM
Foundational and scalable techniques for runtime safety analysis of multithreaded programs are explored in this paper. A technique based on vector clocks to extract the causal dep...
89
Voted
DATE
2009
IEEE
15 years 7 months ago
2009
IEEE
—Redundancy Addition and Removal (RAR) is a restructuring technique used in the synthesis and optimization of logic designs. It can remove an existing target wire and add an alte...
96
Voted
DATE
2008
IEEE
15 years 7 months ago
2008
IEEE
—Latch based circuits are widely adopted in high performance circuits. But there is a lack of accurate latch models for doing timing analysis. In this paper, we propose a new lat...