1534 search results - page 197 / 307 » Error Reporting Logic |
158
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TCAD
1998
15 years 3 months ago
1998
—This paper addresses, from a probabilistic point of view, the issue of switching activity estimation in combinational circuits under the zero-delay model. As the main theoretica...
106
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DAC
2002
ACM
16 years 4 months ago
2002
ACM
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
122
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SIGSOFT
2003
ACM
16 years 4 months ago
2003
ACM
Foundational and scalable techniques for runtime safety analysis of multithreaded programs are explored in this paper. A technique based on vector clocks to extract the causal dep...
115
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DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
—Redundancy Addition and Removal (RAR) is a restructuring technique used in the synthesis and optimization of logic designs. It can remove an existing target wire and add an alte...
127
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DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
—Latch based circuits are widely adopted in high performance circuits. But there is a lack of accurate latch models for doing timing analysis. In this paper, we propose a new lat...