1534 search results - page 24 / 307 » Error Reporting Logic |
FTCS
1994
14 years 11 months ago
1994
This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from Differential Cascode Voltage Switch Logic are...
ITC
2003
IEEE
15 years 3 months ago
2003
IEEE
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
IEEEARES
2007
IEEE
15 years 4 months ago
2007
IEEE
A tool for automated validation of attacks on authentication protocols has been used to find several flaws and ambiguities in the list of attacks described in the well known rep...
ICPR
2002
IEEE
15 years 2 months ago
2002
IEEE
In this paper, a framework for the analysis of the error-reject trade-off in linearly combined classifiers is proposed. We start from a framework developed by Tumer and Ghosh [1,2...
PODS
2007
ACM
15 years 10 months ago
2007
ACM
The contingency table is a work horse of official statistics, the format of reported data for the US Census, Bureau of Labor Statistics, and the Internal Revenue Service. In many ...