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ISQED
2007
IEEE
119views Hardware» more  ISQED 2007»
15 years 4 months ago
Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs
Abstract— Self-calibrating designs have recently gained momentum as an alternative to methods relying on worst-case characterisation of silicon [2], [4], [8]. So far, reliable op...
Frederic Worm, Patrick Thiran, Paolo Ienne
SOSP
2009
ACM
15 years 6 months ago
Debugging in the (very) large: ten years of implementation and experience
Windows Error Reporting (WER) is a distributed system that automates the processing of error reports coming from an installed base of a billion machines. WER has collected billion...
Kirk Glerum, Kinshuman Kinshumann, Steve Greenberg...
DFT
2003
IEEE
117views VLSI» more  DFT 2003»
15 years 3 months ago
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
Sobeeh Almukhaizim, Yiorgos Makris
IQ
2007
14 years 11 months ago
Simulations Of Error Propagation For Prioritizing Data Accuracy Improvement Efforts
: Models of the association between input accuracy and output accuracy imply that, for any given application, the effect of input errors on the output error rate generally varies i...
Irit Askira Gelman
DSD
2007
IEEE
105views Hardware» more  DSD 2007»
15 years 4 months ago
Scaling Analytical Models for Soft Error Rate Estimation Under a Multiple-Fault Environment
With continuing increase in soft error rates, its foreseeable that multiple faults will eventually need to be considered when modeling circuit sensitivity and evaluating faulttole...
Christian J. Hescott, Drew C. Ness, David J. Lilja