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ICCAD
2010
IEEE
148views Hardware» more  ICCAD 2010»
14 years 8 months ago
Trace signal selection to enhance timing and logic visibility in post-silicon validation
Trace buffer technology allows tracking the values of a few number of state elements inside a chip within a desired time window, which is used to analyze logic errors during post-s...
Hamid Shojaei, Azadeh Davoodi
ICLP
2007
Springer
15 years 1 months ago
Web Sites Verification: An Abductive Logic Programming Tool
We present the CIFFWEB system, an innovative tool for the verification of web sites, relying upon abductive logic programming. The system allows the user to define rules that a web...
Paolo Mancarella, Giacomo Terreni, Francesca Toni
AIME
2007
Springer
15 years 4 months ago
Replacing SEP-Triplets in SNOMED CT Using Tractable Description Logic Operators
Reification of parthood relations according to the SEP-triplet encoding pattern has been employed in the clinical terminology SNOMED CT to simulate transitivity of the part-of rel...
Boontawee Suntisrivaraporn, Franz Baader, Stefan S...
DLOG
2008
15 years 11 days ago
Visualization of Description Logic Models
Many visualization frameworks for ontologies in general and for concept expressions in particular are too faithful to the syntax of the languages in which those objects are represe...
Fernando Náufel do Amaral, Carlos Bazilio M...
ISCA
2009
IEEE
159views Hardware» more  ISCA 2009»
15 years 4 months ago
End-to-end register data-flow continuous self-test
While Moore’s Law predicts the ability of semi-conductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in t...
Javier Carretero, Pedro Chaparro, Xavier Vera, Jau...