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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 11 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
15 years 11 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
197
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MICRO
2002
IEEE
164views Hardware» more  MICRO 2002»
15 years 11 months ago
A quantitative framework for automated pre-execution thread selection
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is ineffective. In pre-execution, copies of cache miss computations are isolated fr...
Amir Roth, Gurindar S. Sohi
ICSE
2010
IEEE-ACM
15 years 11 months ago
Test generation through programming in UDITA
We present an approach for describing tests using nondeterministic test generation programs. To write such programs, we introduce UDITA, a Java-based language with non-determinist...
Milos Gligoric, Tihomir Gvero, Vilas Jagannath, Sa...
190
Voted
MICCAI
2001
Springer
15 years 10 months ago
Valmet: A New Validation Tool for Assessing and Improving 3D Object Segmentation
Extracting 3D structures from volumetric images like MRI or CT is becoming a routine process for diagnosis based on quantitation, for radiotherapy planning, for surgical planning a...
Guido Gerig, Matthieu Jomier, Miranda Chakos
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