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ISCA
2007
IEEE
110views Hardware» more  ISCA 2007»
15 years 3 months ago
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities an...
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Par...
100
Voted
EH
2004
IEEE
117views Hardware» more  EH 2004»
15 years 1 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
95
Voted
APCSAC
2007
IEEE
15 years 3 months ago
Runtime Performance Projection Model for Dynamic Power Management
In this paper, a runtime performance projection model for dynamic power management is proposed. The model is built as a first-order linear equation using a linear regression model....
Sang Jeong Lee, Hae-Kag Lee, Pen-Chung Yew
75
Voted
ICDCS
2009
IEEE
15 years 6 months ago
Distributed Processing of Spatial Alarms: A Safe Region-Based Approach
Spatial alarms are considered as one of the basic capabilities in future mobile computing systems for enabling personalization of location-based services. In this paper, we propos...
Bhuvan Bamba, Ling Liu, Arun Iyengar, Philip S. Yu
108
Voted
ISVLSI
2006
IEEE
150views VLSI» more  ISVLSI 2006»
15 years 3 months ago
Design and Analysis of a Low Power VLIW DSP Core
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
Chan-Hao Chang, Diana Marculescu