710 search results - page 100 / 142 » Estimating design time for system circuits |
VLSID
2005
IEEE
16 years 2 months ago
2005
IEEE
In this paper, we present a simple analytical equation for capturing phase errors in 3-stage ring oscillators. The model, based on a simple but useful idealization of the ring osc...
DAC
2009
ACM
15 years 8 months ago
2009
ACM
This paper describes an automatic methodology for optimizing sample point selection for using in the framework of model order reduction (MOR). The procedure, based on the maximiza...
HASE
2007
IEEE
15 years 8 months ago
2007
IEEE
SyncProbe improves the end-to-end predictability of distributed systems by providing applications with a real-time estimate of the maximum expected message delay (upper bound on c...
108
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SLIP
2003
ACM
15 years 7 months ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
147
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DAC
2004
ACM
15 years 5 months ago
2004
ACM
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...