Sciweavers

710 search results - page 101 / 142
» Estimating design time for system circuits
Sort
View
CF
2005
ACM
15 years 3 months ago
Drowsy region-based caches: minimizing both dynamic and static power dissipation
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
PACS
2000
Springer
99views Hardware» more  PACS 2000»
15 years 5 months ago
Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors
Power dissipation is a major concern not only for portable systems, but also for high-performance systems. In the past, energy consumption and processor heating was reduced mainly...
Roberto Maro, Yu Bai, R. Iris Bahar
RTAS
2008
IEEE
15 years 8 months ago
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able t...
Jun Yan, Wei Zhang
DAC
2004
ACM
16 years 2 months ago
Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics
Capacitance extraction is an important problem that has been extensively studied. This paper presents a significant improvement for the fast multipole accelerated boundary element...
Shu Yan, Vivek Sarin, Weiping Shi
MOBIWAC
2006
ACM
15 years 8 months ago
Calibration-free WLAN location system based on dynamic mapping of signal strength
In this work we present a calibration-free system for locating wireless local area network devices, based on the radio frequency characteristics of such networks. Calibration proc...
Luís Felipe M. de Moraes, Bruno Astuto A. N...