710 search results - page 39 / 142 » Estimating design time for system circuits |
DAC
2006
ACM
16 years 23 days ago
2006
ACM
Accurate estimation of the worst-case execution time (WCET) of a program is important for real-time embedded software. Static WCET estimation involves program path analysis and ar...
ET
2007
14 years 11 months ago
2007
This article describes an emulation-based method for locating stuck-at faults in combinational and synchronous sequential circuits. The method is based on automatically designing a...
ASYNC
1998
IEEE
15 years 4 months ago
1998
IEEE
Analogue to digital (A-D) converters with a xed conversion time are subject to errors due to metastability. These errors will occur in all converter designs with a bounded time fo...
CASES
2008
ACM
15 years 1 months ago
2008
ACM
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
ICCAD
2005
IEEE
15 years 8 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...