710 search results - page 46 / 142 » Estimating design time for system circuits |
EH
2004
IEEE
15 years 3 months ago
2004
IEEE
This paper discusses the problem of increased programming time for intrinsic evolvable hardware (EHW) as the complexity of the circuit grows. We develop equations for the size of ...
GECCO
2006
Springer
15 years 3 months ago
2006
Springer
Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. Based on the GPP paradigm and a local search operator - FlowMap, a logic circuit synthesizing system in...
NOCS
2008
IEEE
15 years 6 months ago
2008
IEEE
—Circuit-switched networks can significantly lower the communication latency between processor cores, when compared to packet-switched networks, since once circuits are set up, ...
PATMOS
2005
Springer
15 years 5 months ago
2005
Springer
This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to max...
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MEMOCODE
2006
IEEE
15 years 5 months ago
2006
IEEE
The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the...