710 search results - page 51 / 142 » Estimating design time for system circuits |
125
click to vote
DAC
1998
ACM
15 years 4 months ago
1998
ACM
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
100
click to vote
VTC
2006
IEEE
15 years 5 months ago
2006
IEEE
In this contribution we propose a space-time decision feedback equalization (ST-DFE) assisted multiuser detection (MUD) scheme for multiple antenna aided space division multiple a...
103
click to vote
RECONFIG
2008
IEEE
15 years 6 months ago
2008
IEEE
1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...
DAC
2004
ACM
15 years 5 months ago
2004
ACM
Considering layout effects early in the analog design process is becoming increasingly important. We propose techniques for estimating parasitic capacitances based on look-up tabl...
103
click to vote
CODES
2008
IEEE
14 years 12 months ago
2008
IEEE
With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...