710 search results - page 70 / 142 » Estimating design time for system circuits |
107
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ICCD
2003
IEEE
15 years 8 months ago
2003
IEEE
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
101
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RSP
2005
IEEE
15 years 5 months ago
2005
IEEE
Networks-on-chip (NoCs) are an emergent communication infrastructure, which can be designed to deal with growing system complexity and technology evolution. The efficient use of N...
115
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CDC
2008
IEEE
15 years 6 months ago
2008
IEEE
In this paper we consider Loosely Time-Triggered Architectures (LTTA) as a networked infrastructure for deploying discrete control. LTTA are distributed architectures in which 1/ ...
ISLPED
1997
ACM
15 years 4 months ago
1997
ACM
In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...
132
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ICCD
2008
IEEE
15 years 8 months ago
2008
IEEE
— Run-time Active Leakage Reduction (RALR) is a recent technique and aims at aggressively reducing leakage power consumption. This paper studies the feasibility of RALR from the ...