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» Estimating design time for system circuits
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CODES
2003
IEEE
15 years 5 months ago
A low power scheduler using game theory
In this paper, we describe a new methodology based on game theory for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of schedulin...
N. Ranganathan, Ashok K. Murugavel
DATE
2008
IEEE
103views Hardware» more  DATE 2008»
15 years 6 months ago
Novel Pin Assignment Algorithms for Components with Very High Pin Counts
The wiring effort and thus, the routability of electronic designs such as printed circuit boards, multi chip modules and single chip modules largely depends on the assignment of s...
Tilo Meister, Jens Lienig, Gisbert Thomke
ASAP
2007
IEEE
109views Hardware» more  ASAP 2007»
15 years 1 months ago
Long Live Small Fan-in Majority Gates Their Reign Looks Like Coming!
This paper explores the reliability of three different minimum fan-in majority gates full adder (FA) designs, and compares them to the performance of a standard XOR-based FA. The ...
Walid Ibrahim, Valeriu Beiu
VLSID
2003
IEEE
77views VLSI» more  VLSID 2003»
16 years 8 days ago
A Methodology for Accurate Modeling of Energy Dissipation in Array Structures
There is an increasing need for obtaining a reasonably accurate estimate of energy dissipation in SoC designs. Array structures have a significant contribution to the total system...
Mahesh Mamidipaka, Nikil D. Dutt, Kamal S. Khouri
ICRA
2007
IEEE
201views Robotics» more  ICRA 2007»
15 years 6 months ago
Realtime and Robust Motion Tracking by Matched Filter on CMOS+FPGA Vision System
— This paper describes realtime and robust tracking of a planar motion target by matched filter implemented on the CMOS+FPGA vision system. It is required to obtain positional a...
Kazuhiro Shimizu, Shinichi Hirai