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ICML
2007
IEEE
16 years 18 days ago
Percentile optimization in uncertain Markov decision processes with application to efficient exploration
Markov decision processes are an effective tool in modeling decision-making in uncertain dynamic environments. Since the parameters of these models are typically estimated from da...
Erick Delage, Shie Mannor
IOLTS
2005
IEEE
141views Hardware» more  IOLTS 2005»
15 years 5 months ago
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
ISLPED
1999
ACM
143views Hardware» more  ISLPED 1999»
15 years 4 months ago
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
Kanad Ghose, Milind B. Kamble
VTS
1999
IEEE
83views Hardware» more  VTS 1999»
15 years 4 months ago
PADded Cache: A New Fault-Tolerance Technique for Cache Memories
This paper presents a new fault-tolerance technique for cache memories. Current fault-tolerance techniques for caches are limited either by the number of faults that can be tolera...
Philip P. Shirvani, Edward J. McCluskey
IPPS
1996
IEEE
15 years 4 months ago
A Parallel Algorithm for Minimization of Finite Automata
In this paper, we present a parallel algorithm for the minimization of deterministic finite state automata (DFA's) and discuss its implementation on a connection machine CM-5...
Bala Ravikumar, X. Xiong