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» Estimation of Topological Dimension
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98
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VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
16 years 1 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
112
Voted
CVPR
2010
IEEE
15 years 9 months ago
Combining Discriminative and Generative Methods for 3D Deformable Surface and Articulated Pose Reconstruction
Historically non-rigid shape recovery and articulated pose estimation have evolved as separate fields. Recent methods for non-rigid shape recovery have focused on improving the a...
Mathieu Salzmann, Raquel Urtasun
115
Voted
GLOBECOM
2006
IEEE
15 years 6 months ago
Online Calibration of Path Loss Exponent in Wireless Sensor Networks
— The path loss exponent (PLE) is a parameter indicating the rate at which the received signal strength (RSS) decreases with distance, and its value depends on the specific prop...
Guoqiang Mao, Brian D. O. Anderson, Baris Fidan
92
Voted
CSDA
2006
102views more  CSDA 2006»
15 years 26 days ago
An improved Akaike information criterion for state-space model selection
Following the work of Hurvich, Shumway, and Tsai (1990), we propose an "improved" variant of the Akaike information criterion, AICi, for state-space model selection. The...
Thomas Bengtsson, Joseph E. Cavanaugh
119
Voted
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 6 months ago
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi,...