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MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
13 years 6 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....
BMCBI
2010
118views more  BMCBI 2010»
13 years 6 months ago
Detecting lateral gene transfers by statistical reconciliation of phylogenetic forests
Background: To understand the evolutionary role of Lateral Gene Transfer (LGT), accurate methods are needed to identify transferred genes and infer their timing of acquisition. Ph...
Sophie S. Abby, Eric Tannier, Manolo Gouy, Vincent...
IEEEPACT
2002
IEEE
13 years 11 months ago
Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance
Simultaneous Multithreading (SMT) processors achieve high processor throughput at the expense of single-thread performance. This paper investigates resource allocation policies fo...
Gautham K. Dorai, Donald Yeung
LCTRTS
2007
Springer
14 years 15 days ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...