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TVLSI
2008
164views more  TVLSI 2008»
13 years 6 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
14 years 28 days ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
IJES
2006
110views more  IJES 2006»
13 years 6 months ago
Partitioning bin-packing algorithms for distributed real-time systems
Embedded real-time systems must satisfy not only logical functional requirements but also para-functional properties such as timeliness, Quality of Service (QoS) and reliability. W...
Dionisio de Niz, Raj Rajkumar
HPCN
1997
Springer
13 years 10 months ago
Parallel Simulation of Ion Recombination in Nonpolar Liquids
Abstract. Ion recombination in nonpolar liquids is an important problem in radiation chemistry. We have designed and implemented a parallel Monte Carlo simulation for this computat...
Frank J. Seinstra, Henri E. Bal, Hans J. W. Spoeld...
ISLPED
2004
ACM
139views Hardware» more  ISLPED 2004»
13 years 11 months ago
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
Kim M. Hazelwood, David Brooks