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MICRO
2005
IEEE
139views Hardware» more  MICRO 2005»
15 years 3 months ago
Shader Performance Analysis on a Modern GPU Architecture
This paper presents an analysis of the performance of the shader processing units in a modern Graphics Processor Unit (GPU) architecture using real graphic applications. The archi...
Victor Moya Del Barrio, Carlos González, Jo...
DAC
2002
ACM
15 years 10 months ago
IP delivery for FPGAs using Applets and JHDL
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
Michael J. Wirthlin, Brian McMurtrey
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
15 years 10 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
INFOCOM
2011
IEEE
14 years 1 months ago
Clustering in cooperative networks
Abstract—Low power ad hoc wireless networks operate in conditions where channels are subject to fading. Cooperative diversity mitigates fading in these networks by establishing v...
Boulat A. Bash, Dennis Goeckel, Donald F. Towsley
ECRTS
2004
IEEE
15 years 1 months ago
Schedulability-Driven Partitioning and Mapping for Multi-Cluster Real-Time Systems
We present an approach to partitioning and mapping for multicluster embedded systems consisting of time-triggered and eventtriggered clusters, interconnected via gateways. We have...
Paul Pop, Petru Eles, Zebo Peng, Viacheslav Izosim...