This paper presents an analysis of the performance of the shader processing units in a modern Graphics Processor Unit (GPU) architecture using real graphic applications. The archi...
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Abstract—Low power ad hoc wireless networks operate in conditions where channels are subject to fading. Cooperative diversity mitigates fading in these networks by establishing v...
We present an approach to partitioning and mapping for multicluster embedded systems consisting of time-triggered and eventtriggered clusters, interconnected via gateways. We have...
Paul Pop, Petru Eles, Zebo Peng, Viacheslav Izosim...